(1) Field of the Invention
The present invention relates to the manufacture of ultra large scale integrated (ULSI) circuit chips in general, and in particular, to forming interconnects in a semiconductor substrate by using a borderless dual damascene process having multiple etch-stop layers.
(2) Description of the Related Art
The advantages of borderless contacts or vias are well known in the art. Borders determine to a large extent how closely metal interconnects can be formed in integrated circuits without encroaching on each other. The amount of encroachment or overlap is mitigated by how well lithographic alignment can be achieved between complex structures of metal line and contact interconnects on and in different levels of a semiconductor substrate in which the integrated circuits are formed. The importance of level-to-level alignment gains even more significance as the very large and ultra large scale integration (VLSI and ULSI) of circuits progresses to even smaller feature sizes of less than a micrometer. The present invention discloses a method of forming self-aligned interconnects where borders are no longer needed and hence the packing density of interconnects, that is, that of the integrated circuits can be increased significantly. The disclosed method takes advantage of an improved dual damascene process. The method is equally applicable to either a metal plug formed through a contact hole over a device in a substrate, or through a via hole connecting two metal layers at different levels in a substrate. It will be known to those skilled in the art that contacts refer to an interconnect which interconnects a source-drain device region, salicide of polysilicon to metal, while vias refer to an interconnect which connects metal to metal.
The effect on packing density of borders around contacts is well illustrated by S. M. Sze, et al., in an article published in ULSI Technology. FIGS. 1a, 2c in the drawings, adapted from Sze, show a gain of more than 62% in the packing area in going from a contact having borders to no borders. FIG. 1a shows fully bordered, staggered vias (23) and (33) formed between metal layers (20) and (30. Metal layers have been patterned to form metal lines (27) at the lower level and metal lines (37) on the upper level. Single and double primed reference numerals (27) and (37) refer to other metal lines at the respective levels (20) and (30), respectively. Via (33) on the upper level has border (31) and via (23) on the lower level has its border (21). Ideally, the pitch between metal lines such as (35) for the upper metal lines and (25) for the lower metal lines, is determined by the minimum line and space dimensions that can be patterned using the most recent advances in lithographic techniques. In practice, line pitch is also limited by the via size and the underlying metal pad size forming the border around the via, such as (31) and (21). It will be known by those skilled in the art that a border around a via is needed, for otherwise, grooves would be etched into the underlying insulating layer during the via-etch step, thus causing a thinning of the next level of metal deposited over the via. The minimum dimension by which the metal pad must frame the via, that is, form a border, is dependent on the misalignment tolerances of the lithography step.
Furthermore, the slope of the via wall must be taken into account when determining the minimum pitch between vias. Sloped walls are needed so that the vias can be filled more easily with metal, and without any voids inside the via holes. Also, appropriate slope is needed for adequate metal coverage over the step of the edge of the via hole when physical vapor deposition is employed. The step coverage is in turn dependent upon the aspect ratio, that is, depth over the width of the via hole. A cross-sectional view of vias (55) and (65) with sloped walls (57) and (67), respectively, is shown in FIG. 1b. It will be noted that the more is the slope of the via wall, the larger the border must be for the metal pad over the lower via to insure full coverage of the via.
It is also noted that the vias of FIG. 1a and FIG. 1b are formed laterally with respect to each other. That is, they are staggered rather than being stacked on top of one another as shown in FIG. 1c. The pitch between staggered vias can be reduced if the borders around the vias can also be reduced. The borders can be reduced if the slope of the walls can be reduced. The slope can be reduced if the holes can be filled properly with walls approaching vertical orientation. As is known in the art, forming metal plugs, such as tungsten plugs, in via holes separate from forming metal lines makes vertical vias possible. Plug forming methods are advantageous also in filling contact or via holes of different cross-sectional areas, though they may not fill the openings up to the top. This is shown by reference numerals (75) and (85) in FIG. 1c where vias (73) and (83) have more steeply sloped walls, and they span, respectively, insulation layers (70) and (80).
Contacts and vias with vertical walls, and with no borders, can also be made, as disclosed later in this invention and as depicted in FIG. 2a. Though the interconnects in FIGS. 2a-2b pertain to vias between metal layers in a substrate, it will be obvious to those skilled in the art that the same approach will apply to contact interconnects that are formed to make connections with the devices formed in the semiconductor substrate.
Thus, vertical vias and/or contacts (93) and (103) are formed in insulating layers (90) and (100), respectively. In the case of vias, shown in FIG. 2b, they connect two metal layers (97) and (107). Thus, the minimum distance, such as (25') and (35') in FIG. 2b, between adjacent metal lines, is reduced since the vias have no slope. Secondly, the borders are no longer needed, since plugs (23), (33) in the completely filled vias provide ample overetch protection to underlying metal structures without mask coverage, as it will be appreciated by those skilled in the art. Even with borderless contacts and vias only, then, there is substantial reduction in the area occupied by these vias as shown in FIG. 2b in comparison with vias with borders of FIG. 1a. Hence, the pitch (35') between adjacent lines (37) and (37') can be reduced . The line pitch can be further reduced if the vias are stacked on top of one another as shown in FIG. 2c where upper vias (23), (23') and (23") are stacked on top of lower vias (33), (33') and (33"), thus significantly reducing upper metal line pitch from (35) to (35"), and lower metal line pitch from (25) to (25"). Hence, significant gains in packing density can be achieved with stacked and borderless contacts or vias.
However, the practice of stacking contacts and borderless contacts is still in its infancy, as observed by Sze in the earlier Reference. Conventionally, the metal layers and the interconnecting layers are formed separately, and serially. First, a first blanket metal is deposited on a first insulating layer and electrical lines are formed by subtractive etching of the metal through a first mask. A second insulating layer is formed over the first metallized layer, and the second insulating layer is patterned with contact or via holes using a second mask. The holes are then filled with metal, thus forming metal columns, or plugs, contacting the first metal layer. A second blanket metal layer is formed over the second insulating layer containing the columnar plugs which now connect the upper second metal layer with the lower first metal layer. The second metal layer is next patterned with another mask to form a set of new metal lines, and the process is repeated as many times as it is needed to fabricate a semiconductor substrate. With this conventional process, lithographic alignment tolerances must be held very tight in order to form reliable borderless contacts or vias.
On the other hand, forming plugs and metal lines simultaneously, as in the modified dual damascene process disclosed in this invention, some of the misalignment problems can be overcome. In the standard dual damascene process the insulating layer is coated with a resist material which is exposed to a first mask with the image pattern of the via opening and the pattern is anisotropically etched in the upper half of the insulating layer. After removal of the patterned resist material, the insulating layer is coated with another resist material which is exposed to a second mask with image pattern of the conductive lines in alignment with the via openings. In anisotropically etching the openings for the conductive line in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched in the lower half of the insulating material. After the etching is complete, both the vias and grooves are filled with metal. Though the alignment of contact or via holes with respect to the metal lines is improved, the standard dual damascene is still difficult to practice in forming borderless contacts and vias for metal pitches of sub-half micron, and with copper metal.
Shoda in U.S. Pat. No. 5,529,953 uses a dual damascene process with selective deposition in forming interconnects in a multi-layered semiconductor device. His method teaches forming a line trench including a first opening portion and a second opening portion in a dielectric layer, forming a first adhesion layer on a surface exposed by the first opening portion, forming a second adhesion layer on a surface exposed by the second opening portion, and selectively depositing a conductive material on the first adhesion layer and the second adhesion layer, wherein growth of the conductive material on the second adhesion layer starts after growth of the conductive material on the first adhesion layer has stared. The first and second adhesion layers are of different materials. Zettler, et al., (U.S. Pat. No. 5,422,309) teach the forming of a metallization level having contacts and interconnects connecting the contacts. Here, an insulating layer wherein contact holes to regions to be contacted are opened is applied surface-wide onto a substrate. For producing an interconnect mask, a photoresist layer is applied, exposed and developed such that the surface of the regions to be contacted remains covered with photoresist in exposed regions, whereas the surface of the insulating layer is uncovered in the exposed regions. Using the interconnect mask as etching mask, trenches are etched into the insulating layer. Contacts and interconnects of a metallization level are finished by filling the contact holes and the trenches with metal. Havemann in U.S. Pat. No. 5,565,384 uses a low permittivity dielectric in forming self-aligned vias. These prior art methods differ from the present invention where two etch-stop layers are used to form borderless contact and via interconnects with a modified and improved dual damascene process.